(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for the improvement of low-k dielectric material structural strength by creating a dummy plug having good plug fill uniformity.
(2) Description of the Prior Art
The creation of semiconductor devices frequently comprises creating patterns of conducting interconnect lines, which is typically a combination of the deposition of layers of dielectric and layers of conductive materials such as metal. The deposited layers of metal are patterned and etched, forming one or more layers of interconnect traces in or over the layers of dielectric.
The continuing effort to reduce the size of individual transistors and other devices commonly integrated on a semiconductor chip and to increase the density of Integrated Circuits results in a continuing reduction of the separation between conducting layers of materials. To further enhance semiconductor device performance, the use of low-k dielectric constant dielectric materials is of advantage. For instance, the parasitic capacitance between adjacent conducting lines is highly dependent on the dielectric constant of the insulator or dielectric used to separate the conducting lines. Conventional semiconductor fabrication typically uses silicon dioxide as a dielectric; this has a dielectric constant of about 3.9. The lowest possible and therefore the ideal dielectric constant is 1.0, this is the dielectric constant of a vacuum whereas air has a dielectric constant of slightly larger than 1.0.
The use of many of the low dielectric constant materials is not feasible due to the fact that equipment is not available to properly process the new dielectric material in various integrated circuits. Also, the chemical or physical properties of many low dielectric constant materials are usually difficult to make compatible with or integrate into conventional integrated circuit processing.
A major objective in the design of Integrated Circuit (IC) devices is to reduce the dielectric constant (k) of the insulating layer between adjacent conductor lines of semiconductor circuits. With the reduction in device dimensions, overlying layers of insulation are accordingly reduced in thickness while more layers of interconnect traces are created as overlying layers. From this results the need for good surface planarity (flatness), a requirement that particularly applies to the lower layers of a stack of overlying layers since lack of planarity in the lower layers is emphasized and has an increasingly more severe detrimental effect as the number of overlying layers increases. For this reason of flattening a surface, conventional technology provides methods for forming dummy patterns that are aimed at enhancing the planarity of individual layers of a stack of overlying layers and therewith the planarity of the total structure. The dummy patterns may comprise patterned layers of metal or dummy plugs. Openings for dummy plugs that are created for the purpose of enhancing the ability to create multiple overlying layers of interconnect metal typically are etched through a layer of insulating material thereby stopping on the surface of an etch stop layer. This creates an interface between the dummy plugs and the underlying layer of etch stop material, which is characterized by weak mechanical bonding between the layer of etch stop material and the dummy plug. It is well known in the art that low-k dielectric materials typically have low thermal conductivity making these materials more susceptible to dielectric cracking and delamination under and around interfaces with for instance dummy plugs. The dummy plug is therefore prone to “shift” over the surface of the layer of etch stop material, resulting in an unstable structure of overlying layers of insulation material and therein or there-over created networks of interconnect metal. The invention addresses this concern by providing dummy plugs that are firmly anchored within the structure of interconnect metal.
U.S. Pat. No. 6,103,626 (Kim) shows a method for forming dummy pattern areas in a semiconductor device.
U.S. Pat. No. 6,259,115 (You, et al.) teaches a method for inserting dummy conductive channels along with the interconnected conductive channels. The dummy channels have an approximately even metal weight distribution.
U.S. Pat. No. 6,150,232 (Chan, et al.) discloses a method for creating low intra-level dielectric interface between conducting lines using conventional deposition and etching processes. A layer of conducting lines is formed interspersed with dielectric material.
U.S. Pat. No. 6,087,733 (Maxim, et al.) shows sacrificial erosion control features for chemical-mechanical polishing process.